During the formation of semiconductor devices such as dynamic random access memories (DRAM), static random access memories (SRAM), logic devices, and microprocessors, several structures are commonly formed. For example, parallel metal lines such as data lines as well as other conductive interconnects and buses are formed to provide an electrical pathway, for example a pathway for data bits to and from storage capacitors on a semiconductor memory device. As a goal in semiconductor device design is to minimize device dimensions and maximize density, many of the conductive lines are formed in close proximity to adjacent lines. Contrary to this goal is the effect of capacitive coupling between adjacent lines. To reduce capacitive coupling, the spacing between lines must be sufficiently wide to ensure any electrical effects created by the coupling are minimized so that incorrect data, clock and signal timing problems, power draw due to capacitor coupling, signal noise corruption, and device lockup do not result.
A method used during the formation of a semiconductor device which allows for closer formation of device features, and the structure having increased feature density which results therefrom, would be desirable.